1. Field of the Invention
The present invention generally relates to an operation method of a memory, and more particularly, to an operation method of a non-volatile memory for reducing the second-bit effect in the non-volatile memory.
2. Description of Related Art
Due to the advantages of saving, reading and clearing data time after time and still keeping the saved data after cutting power, a non-volatile memory becomes the irreplaceable one in many electric products so as to keep the electric products for normal operations during turning on. Therefore, a non-volatile memory serves as a memory device is broadly used in PCs and electronic equipments.
Among various non-volatile memories, a nitride read only memory (Nbit) is the one based on a charge trapping for storing data. The structure of an Nbit memory cell is just like a metal-oxide-silicon field effect transistor (MOS-FET) except that the gate silicon oxide layer of an MOS-FET is substituted by an ONO layer (oxide-nitride-oxide layer), wherein the silicon nitride material is characteristic of trapping charges (electrons) when the Nbit memory cell is programmed. In order to program (i.e., to inject charges) the charge-trapping layer of an Nbit memory cell, many kinds of processes of hot carrier injection can be used, for example, a process of channel hot electron injection (CHE) or a process of source side injection (SSI). In addition, a process of channel initiated  secondary electron (CHISEL) can be used to program the charge-trapping layer of an Nbit memory cell as well. A localized implementation of charge trapping technique allows each Nbit memory cell having two separated charge bits so as to form a so-called 2 bits/cell as a memory.
To judge the physically separated charges at the two sides of an Nbit memory cell, reverse read scheme is adopted. The reverse read scheme means reading operation is done by applying a reading bias to Source terminal to sense the charges above the Drain-side junction, and vice versa. The reading bias is enough high so that it can screen out the influence of the charges above the Source-side junction if there are. However, whenever operating an Nbit memory cell stored by 2-bits, the two bits of the same memory cell might still affect each other to cause troubles. In short, if a bit has stored at one-side of an Nbit memory cell, then, a reading operation for the other portion of the cell with an expected high current would have current-dropping phenomena, called second-bit effect. In other words, when conducting a reading operation on the memory cell, the present bit would affect the memory cell, which raises up the barrier and thereby increases the threshold voltage (Vt) for reading. Consequently, a reading error may occur.
FIG. 1A is a diagram showing a Vt distribution of a conventional 2-bits memory cell. Referring to FIG. 1A, when the level of the second bit is a higher level (“0”), the second-bit effect makes the Vt distribution of the cell drifted so as to narrow the operation window, wherein the first bit of the cell has been at the state “1” already. As a result, when reading the memory cell, the level “1” of the first bit thereof may be misjudged as the level “0”.
In addition, the memory size is larger and larger along with increasing sizes of  application software of a computer. Therefore, the conventional memory device for storing a bit or two bits can not satisfy the current demands. In this regard, a memory device able to store multi-bits data was provided in recent years, which is termed as a multi-level memory. On the other hand, an Nbit memory cell can serve as a multi-level memory cell (MLC) by setting a plurality of programming verification levels at the two bits thereof. For an MLC however, a more accurate Vt distribution scope is required, which results in a more complicate operation. Besides, the above-mentioned second-bit effect can also occur in an MLC.
FIG. 1B is a diagram showing a Vt distribution of an MLC. Referring to FIG. 1B, when data (with a higher level) is stored at a second storage position of an MLC, the so-called second-bit effect may affect the first storage position; in particular, the higher the level of the second storage position, the more serious the second-bit effect would be. For example, when the second storage position has the highest level (“4”), the second-bit effect may make the Vt distribution of the memory cell drifted so that the drifted Vt distribution is very close to the Vt distribution of the memory cell of being programmed into the state “2”, wherein the first storage position thereof has the level state “1”. Since the drifted Vt distribution is very close to that of the memory cell of being programmed into the level state “2”, the operation window is narrowed. As a result, when reading the memory cell, it is possible to misjudge the level “1” of the first storage position of the memory cell as the level “2”.
As described above, the second-bit effect not only results in the operation difficulty on the memory device, but also reduces the reliability thereof. The second-bit effect further reduces the sensing margin and the Vt window for operating the left and right  two bits, which makes the operation of a multi-level memory more difficult.